In silicon (Si) based microelectronics, a key parameter in assessing device performance is the current delivered at a given design voltage. This parameter is commonly referred to as transistor drive current or saturation current (IDsat). Drive current is affected by factors that include the transistor's channel mobility and external resistance.
Channel mobility refers to the mobility of carriers (i.e. holes and electrons) in the transistor's channel region. Increased carrier mobility translates directly into increased drive current at a given design voltage and gate length. Carrier mobility can be increased by straining the channel region's silicon lattice. For n-MOS devices, carrier mobility (i.e. electron mobility) can be enhanced by generating a tensile strain in the transistor's channel region.
Drive current is also influenced by other factors that include: (1) the resistances associated with the ohmic contacts (metal to semiconductor and semiconductor to metal), (2) the resistance within the source/drain region itself, and (3) the resistance of the region between the channel region and the source/drain regions (i.e. the tip region). The sum of these resistances is commonly referred to as the external resistance.
A global approach to increasing n-MOS transistor performance (by generating tensile channel strain) incorporates use of a silicon germanium (SiGe) layer formed over the entire surface of a semiconductor substrate. Epitaxial silicon that is grown on the SiGe layer will strain as it attempts to maintain its silicon crystal structure. Limitations with respect to this approach include: (1) an inability to generate high levels of tensile strain, (2) high dislocation defect densities, (3) the cost and complexity of the SiGe integration scheme, and (4) the production of an offsetting decrease in hole mobility that can degrade p-MOS transistor performance.
Local straining, as compared to global straining, focuses on the optimization of individual transistors by generating a particular type of strain in specific regions of the semiconductor substrate. Current methods for locally straining transistor channel regions include selective epitaxial deposition of source and drain regions with materials that impart a compressive strain in a p-MOS transistor's channel region and deposition of a strained dielectric layer above the gate stack to impart a tensile strain in an underlying n-MOS transistor's channel region.
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